Grade 13 — Term 2
8 study notes · 97 practice questions · Aligned with NIE syllabus
Counted in the Idasara Academy app, which you open with a free account. The free notes, revision, practice and library pages for each lesson are linked below.
This term in the Idasara Academy app has 8 lessons (NIE Unit 9). For each lesson, this page gives you the points you must know and one exam-style question with its answer. None of it needs an account.
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Lessons in This Term
Semiconductors & p–n Junctions
What you must know
- Biasing Effects on Depletion Layer: Forward Bias (p connected to +, n connected to -): External field opposes internal barrier field, narrowing depletion layer, reducing barrier height, permitting heavy exponential majority carrier forward current; Reverse Bias (p connected to -, n connected to +): External field reinforces barrier field, widening depletion layer, blocking majority flow.
- Reverse Saturation Current (I_s): In reverse bias, a minute leakage current (~nanoamperes in Si, microamperes in Ge) flows due to thermally generated minority carriers swept across junction; strongly temperature dependent.
- Electrical Neutrality of Doped Semiconductors: Despite being called n-type and p-type, the bulk materials remain electrically NEUTRAL overall because donor and acceptor atoms were originally neutral.
Try one question
What type of extrinsic semiconductor is produced when an intrinsic crystalline silicon wafer (Group IV) is doped with trivalent impurity atoms such as Indium or Boron (Group III)?
- A. p-type semiconductor with holes as majority charge carriers
- B. n-type semiconductor with conduction electrons as majority charge carriers
- C. Intrinsic semiconductor with zero electrical conductivity
- D. Superconducting ceramic compound
Show the answer
Answer: A. p-type semiconductor with holes as majority charge carriers. Doping silicon with Group III elements creates acceptor energy levels just above the valence band. Each trivalent atom shares 3 valence electrons, leaving one unfilled covalent bond—a hole. Hence, holes become the majority charge carriers, yielding a p-type semiconductor.
A model question written by Idasara on the exam pattern. It is not from a past paper.
Diodes & Rectification
What you must know
- Capacitor Smoothing Filter: Shunt smoothing capacitor C connected in parallel across load resistor RL charges to peak voltage Vm and discharges slowly between peaks with time constant τ = RL * C; larger C produces smoother, flatter DC output with minimal ripple voltage.
- Bridge Rectifier Conduction Path: During positive half-cycle, diodes D1 and D3 conduct in series; during negative half-cycle, D2 and D4 conduct; current flows through load resistor RL in the IDENTICAL direction during both half-cycles.
- Diode Protection: A current-limiting resistor must always be connected in series with a diode to prevent catastrophic thermal destruction when conducting in forward bias.
Try one question
A full-wave bridge rectifier using four ideal p-n junction diodes is fed by a 50 Hz sinusoidal alternating current mains supply. What is the fundamental ripple frequency of the rectified direct-current output voltage?
- A. 200 Hz
- B. 25 Hz
- C. 50 Hz
- D. 100 Hz
Show the answer
Answer: D. 100 Hz. In a full-wave rectifier, both the positive and negative half-cycles of the AC input are converted into unidirectional output pulses. Since two output pulses occur per single AC input cycle, the output ripple frequency is double the input frequency: f_ripple = 2 × f_in = 2 × 50 Hz = 100 Hz.
A model question written by Idasara on the exam pattern. It is not from a past paper.
Zener Diodes & Regulation
What you must know
- Series Resistance Selection (Rs): Must satisfy Rs = (Vin - Vz) / (Iz + IL); Rs must be small enough to maintain minimum Zener knee current Iz_min at maximum load current IL_max, yet large enough that Zener power dissipation does not exceed maximum rated power Pz_max = Vz * Iz_max when load is disconnected (IL = 0).
- Condition for Regulation: Regulation is maintained strictly as long as Vin > Vz and Zener current Iz remains between Iz_min (knee current) and Iz_max (thermal limit).
- Dynamic (Zener) Resistance rz: rz = ΔVz / ΔIz; ideal Zener diode has rz = 0 (perfectly vertical I-V breakdown curve).
Try one question
In a voltage regulator circuit, how must a Zener diode be connected relative to the unregulated DC input voltage, and in which operating region does it maintain a nearly constant terminal voltage?
- A. In forward bias in series with the load, operating in the forward conduction region
- B. In forward bias across the load, operating in the saturation region
- C. In reverse bias in series with the load, operating below the knee voltage
- D. In reverse bias across the load, operating in the reverse breakdown (Zener breakdown) region
Show the answer
Answer: D. In reverse bias across the load, operating in the reverse breakdown (Zener breakdown) region. A Zener diode is designed to operate in reverse bias beyond its breakdown voltage (V_Z). In this reverse breakdown region, the diode current can vary widely while the voltage across its terminals remains virtually constant, providing excellent voltage stabilization across a parallel load.
A model question written by Idasara on the exam pattern. It is not from a past paper.
Bipolar Junction Transistors (BJT)
What you must know
- Common Emitter (CE) Voltage Amplifier: Input applied between base and emitter, output taken between collector and emitter; provides high voltage gain Av = - (Rc / r_in) * β and 180° (π radians) phase inversion between input and output waveforms.
- Base-Emitter forward drop: In active/saturation mode for Silicon BJT, Vbe remains strictly constant at approximately 0.7 V.
- Transistor as a Switch: Driven between Cut-off (V_in = 0, Ib = 0, Vce = Vcc, OFF state) and Saturation (V_in high, Ib > Ic_sat / β, Vce = Vce_sat ≈ 0.2 V, ON state).
Try one question
In a common-emitter (CE) bipolar junction transistor (BJT) amplifier circuit, a small change in base current ΔI_B = 20 μA produces a corresponding change in collector current ΔI_C = 2.0 mA. What is the common-emitter forward current gain (β)?
- A. 50
- B. 200
- C. 100
- D. 0.99
Show the answer
Answer: C. 100. The common-emitter current gain β (also denoted h_fe) is defined as the ratio of change in collector current to change in base current: β = ΔI_C / ΔI_B. Substituting: β = (2.0 × 10⁻³ A) / (20 × 10⁻⁶ A) = 2.0 × 10⁻³ / 0.020 × 10⁻³ = 100.
A model question written by Idasara on the exam pattern. It is not from a past paper.
Field Effect Transistors (FET/JFET/MOSFET)
What you must know
- BJT vs FET Key Differences: BJT is bipolar (conduction by both electrons and holes) and CURRENT-controlled; FET is unipolar (conduction solely by majority carriers) and VOLTAGE-controlled with far higher input impedance and lower thermal noise.
- Shockley's Equation for JFET: In the active/saturation region: Id = Idss * [1 - (Vgs / Vp)]², where Idss is drain saturation current at zero gate bias and Vp is pinch-off voltage.
- Static Electricity Sensitivity of MOSFETs: The ultra-thin SiO2 gate oxide insulation can easily be punctured and permanently destroyed by electrostatic discharge (ESD) from human hands; stored in conductive antistatic foam.
Try one question
What is the primary operational distinction between a Field Effect Transistor (FET) and a Bipolar Junction Transistor (BJT)?
- A. FET is a unipolar voltage-controlled device with extremely high input impedance, whereas BJT is a bipolar current-controlled device
- B. FET has zero pinch-off voltage and negative breakdown resistance
- C. BJT utilizes only majority carriers, whereas FET utilizes both electrons and holes simultaneously
- D. BJT has infinite gate resistance, whereas FET requires high continuous gate current
Show the answer
Answer: A. FET is a unipolar voltage-controlled device with extremely high input impedance, whereas BJT is a bipolar current-controlled device. A FET is a unipolar device wherein conduction is governed by one type of carrier (electrons in n-channel, holes in p-channel) controlled by the electric field (gate voltage V_GS), yielding nearly infinite input impedance. BJTs are current-controlled (I_B governs I_C) and rely on both electrons and holes (bipolar).
A model question written by Idasara on the exam pattern. It is not from a past paper.
Operational Amplifiers (Op‑Amps)
What you must know
- Op-Amp Comparator (Open-Loop): Without feedback, op-amp compares V+ and V-: If V+ > V-, output saturates at positive rail +Vsat (≈ +Vcc - 1.5 V); If V+ < V-, output saturates at negative rail -Vsat; used in light-activated relays, temperature controllers, and ADC converters.
- Virtual Ground concept in Inverting Amplifier: Since non-inverting terminal is tied to 0 V (ground), negative feedback drives inverting node to 0 V (V- = 0 V); this node acts as a 'Virtual Ground' that sinks current without being physically wired to ground.
- Output Saturation Limits: Output voltage cannot exceed supply rails: -Vcc ≤ Vout ≤ +Vcc.
Try one question
In an ideal operational amplifier connected in an inverting amplifier configuration, the input resistor is R_in = 10 kΩ and the feedback resistor is R_f = 100 kΩ. What is the closed-loop voltage gain (A_v) of the amplifier?
- A. +10
- B. -10
- C. -0.1
- D. +11
Show the answer
Answer: B. -10. For an ideal inverting operational amplifier, the inverting terminal is held at virtual ground (0 V). The closed-loop voltage gain is given by A_v = V_out / V_in = - R_f / R_in = - 100 kΩ / 10 kΩ = -10 (the negative sign indicates a 180° phase inversion).
A model question written by Idasara on the exam pattern. It is not from a past paper.
Logic Gates & Boolean Algebra
What you must know
- Exclusive-OR (XOR) & XNOR Gates: XOR: Y = A ⊕ B = Ā B + A B̄ (output 1 when inputs are DIFFERENT; used in binary adders and parity checkers); XNOR: Y = A ⊙ B = A B + Ā B̄ (output 1 when inputs are IDENTICAL).
- Synthesis of NOT from NAND: Tie both inputs of a 2-input NAND gate together: Y = (A · A)̄ = Ā.
- Redundancy / Absorption Rules in Boolean Algebra: A + A·B = A; A + Ā·B = A + B; A · (A + B) = A; A · (Ā + B) = A · B.
Try one question
According to De Morgan's first theorem of Boolean algebra, what is the simplified equivalent expression for the complement of a logical sum, NOT(A OR B)?
- A. A' · B' (NOT A AND NOT B)
- B. A + B
- C. A · B
- D. A' + B' (NOT A OR NOT B)
Show the answer
Answer: A. A' · B' (NOT A AND NOT B). De Morgan's First Theorem states that the complement of a logical disjunction (OR) is equivalent to the conjunction (AND) of the complements: (A + B)' = A' · B'. (The NOR gate is logically equivalent to an active-low input AND gate).
A model question written by Idasara on the exam pattern. It is not from a past paper.
Flip‑Flops & Sequential Logic
What you must know
- Edge-Triggered vs Level-Triggered: Level-triggered latches respond continuously while clock pulse is HIGH; Edge-triggered flip-flops respond strictly on the instantaneous transition (rising positive edge or falling negative edge) of the clock signal.
- Frequency Division via T-Flip-Flop: Connecting JK flip-flop in toggle mode (J = K = 1) divides the clock frequency by 2: f_out = f_clock / 2; cascading N toggle flip-flops yields an N-bit binary ripple counter dividing frequency by 2^N.
- Shift Registers: Cascaded chain of D flip-flops sharing a common clock; shifts binary data bit-by-bit sequentially for serial-to-parallel and parallel-to-serial conversion.
Try one question
In digital electronics, what fundamental characteristic distinguishes sequential logic circuits (such as flip-flops and registers) from combinational logic circuits?
- A. Sequential circuits can only be constructed using vacuum tubes rather than semiconductor transistors
- B. Sequential circuits contain memory elements whose current output depends on both current inputs and past states
- C. Sequential circuits have zero propagation delay and infinite frequency response
- D. Sequential circuits depend solely on present instantaneous inputs without any feedback or clock signals
Show the answer
Answer: B. Sequential circuits contain memory elements whose current output depends on both current inputs and past states. Combinational circuits have outputs determined entirely by the instantaneous values of their present inputs (memoryless). Sequential circuits incorporate memory elements (flip-flops) and feedback loops, so that their present output depends on both current inputs and the internal stored past history (states).
A model question written by Idasara on the exam pattern. It is not from a past paper.
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